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An interrupt that occurs when a program requests data that is not currently in real memory. The interrupt triggers the operating system to fetch the data from a virtual memory and load it into RAM. An invalid page fault or page fault error occurs when the operating system cannot find the data in virtual memory. This usually happens when the virtual memory area, or the table that maps virtual addresses to real addresses, becomes corrupt. A page fault is a trap to the software raised by the hardware when a program accesses a page that is mapped in the virtual address space, but not loaded in physical memory. The hardware that detects a page fault is the memory management unit in a processor. The exception handling software that handles the page fault is generally part of the operating system. Types of Page Faults 1. Minor If the page is loaded in memory at the time the fault is generated, but is not marked in the memory management unit as being loaded in memory, then it is

A page is a sequence of N bytes where N is a power of 2. Let's assume that we have 1M of RAM. RAM is also called physical memory. We can subdivide the RAM into 4K pages. Thus 1M / 4K = 256 pages.  Thus, our RAM has 256 physical pages, each holding 4K. Fig 1: Address translation from virtual to physical Page Table How is an address translated from virtual to physical? Fig 2: Page Table First, like the cache, we split up a 32 bit virtual address into a virtual page (which is like a tag) and a page offset. We must convert the virtual page number to a physical page number. For example, The virtual page consists of 20 bits.  A page table is a data structure which consists of 2 20 page table entries (PTEs).  The page table as an array of page table entries, indexed by the virtual page number. The page table's index starts at 0, and ends at 2 20 - 1. Suppose your program generates a virtual address. You'd extract bits B 31-12 to get the virtual p

If you think it’s there, and it’s there…it’s real. If you think it’s not there, and it’s there…it’s transparent. If you think it’s there, and it’s not there…it’s imaginary. If you think it’s not there, and it’s not there…it’s nonexistent. Virtual memory is imaginary memory: it gives you the illusion of a memory arrangement that’s not physically there. If your computer lacks the random access memory (RAM) needed to run a program or operation, Windows uses virtual memory to compensate. Virtual memory combines your computer’s RAM with temporary space on your hard disk.  When RAM runs low, virtual memory moves data from RAM to a space called a paging file .  Moving data to and from the paging file frees up RAM to complete its work. You can think of virtual memory as an alternate set of memory addresses. Programs use these virtual addresses rather than real addresses to store instructions and data. When the program is actually executed, the virtual addresses are c

A multilevel cache hierarchy consists of n levels of caches. C1, C2, .......,Ci,....... Cn. A processor reference is serviced by the cache closest to the processor that contains the data.  At the same time that cache provides information to the caches on the path between itself and the processor. Multilevel cache hierarchy for multi- processors neither a local LRU nor a global LRU. Where all references to a Ci cache are percolated to its parent for rear-ranging the LRU stack at the Ci+i level. Multilevel caches Another issue is the fundamental tradeoff between cache latency and hit rate.  Larger caches have better hit rates but longer latency. To address this tradeoff, many computers use multiple levels of cache, with small fast caches backed up by larger, slower caches. Multi-level caches generally operate by checking the smallest level 1 (L1) cache first. If it hits, the processor proceeds at high speed.  If the smaller cache misses, the next larger cache (L2) is c

Cache memory Operations in Cache Memory Multilevel Cache Memory

The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere.  If requested data is contained in the cache ( cache hit ), this request can be served by simply reading the cache, which is comparatively faster. Otherwise (cache miss), the data has to be recomputed or fetched from its original storage location, which is comparatively slower. To be cost efficient and to enable an efficient use of data, caches are relatively small. References exhibit temporal locality if data is requested again that has been recently requested already. References exhibit spatial locality if data is requested that is physically stored close to data that has been requested already. Cache operation CPU requests contents of memory location. Check cache for this data. If present, get from cache (fast). If not present, read required block from main memory to cache. Then deliver from cache to CPU. Cache includes

Data Structures and Algorithms Computer Architecture Operation Research Object Oriented Software Engineering Computer Networks

Anna University Questions (reg: 2009)-ME CSE CS9212 DATA STRUCTURES AND ALGORITHMS QUESTION PAPER JAN 2010 CS9212 DATA STRUCTURES AND ALGORITHMS QUESTION PAPER  JUNE 2010 CS9212 DATA STRUCTURES AND ALGORITHMS QUESTION PAPER DEC 2010 CS9212 DATA STRUCTURES AND ALGORITHMS QUESTION PAPER Jan 2013 CS9212 DATA STRUCTURES AND ALGORITHMS QUESTION PAPER JUNE/JULY 2013  

Anna University Questions (reg: 2009)-ME CSE CS9211 COMPUTER ARCHITECTURE QUESTION PAPER JAN 2010 CS9211 COMPUTER ARCHITECTURE QUESTION PAPER JUNE 2010 CS9211 COMPUTER ARCHITECTURE QUESTION PAPER NOV/DEC 2010

Anna University Questions (reg: 2009)-ME CSE MA9219 OPERATION RESEARCH MA9219 OPERATION RESEARCH QUESTION PAPER JAN 2010 MA9219 OPERATION RESEARCH QUESTION PAPER JUNE 2010 MA9219 OPERATION RESEARCH QUESTION PAPER DEC 2010 NON MARKOVIAN QUEUES &QUEUE NETWORKS Questions Unit II

Anna University Questions (reg: 2009)-ME CSE SE9213 OBJECT ORIENTED SOFTWARE ENGINEERING QUESTION PAPER JAN 2010 SE9213 OBJECT ORIENTED SOFTWARE ENGINEERING QUESTION PAPER JUNE 2010

Anna University Chennai EC2352 computer networks question bank CS9213 COMPUTER NETWORKS AND MANAGEMENT (ME CSE) EC2352 COMPUTER NETWORKS QUESTIONS (BE EC )

Anna University CS9213 COMPUTER NETWORKS AND MANAGEMENT QUESTION PAPERS JAN 2010 CS9213 COMPUTER NETWORKS AND MANAGEMENT QUESTION PAPERS JUNE 2010

Anna University Questions (reg: 2008/2010) EC2352 COMPUTER NETWORKS QUESTION PAPER MAY/JUNE 2013 EC2352 COMPUTER NETWORKS QUESTION BANK

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK      S YEAR:  IIIrd  year  ‘B’  Sec       SEMESTER  :  VI UNIT-I PHYSICAL LAYER  PART-A (2 Marks) What are the five  important components of data communication?   List two advantages of layering principle in computer networks. ?   With the example explain half duplex communication. ?   Mention any two functions of  session layer. ?   Name four topologies of computer networks. ?   Suggest two points to improve the  performance of network. ?   With the example explain half duplex communication. ?   Define protocol.   ? Differentiate guided and  unguided media.   ?  What is the Null  modem?    Define T opology. ?   Define standards?    What are the design factors for  transmission media?   Difference between Guided media and un  guided media?   Define line coding?   What are most popular modems?   Define network? What are the criteria for networks for networks? Define point

A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory.  The cache is a smaller, faster memory which stores copies of the data from frequently used main memory locations.  As long as most memory accesses are cached memory locations, the average latency of memory accesses will be closer to the cache latency than to the latency of main memory. An L1 cache is on the same chip as the microprocessor. L2 is usually a separate static RAM (SRAM) chip.  The main RAM is usually a dynamic RAM (DRAM) chip. Cache entries Data is transferred between memory and cache in blocks of fixed size, called cache lines. When a cache line is copied from memory into the cache, a cache entry is created.  The cache entry will include the copied data as well as the requested memory location (now called a tag). When the processor needs to read or write a location in main memory, it first checks for a corresponding entry in the cache.  Th

A memory chip is an electronic component in which a program, data or both can be stored. The program / data are stored in the memory chip as a series of numbers - zeros and ones (=bits).  A bit can be either a zero or a one.  Sixteen bits are a "word", eight bits are a "byte" and four bits are a "nibble". ORGANIZATION OF A MEMORY CHIP For the 8 bit memory chips (the most common type) the bits are put together in a byte (= 8 bits) and stored under an "address". The bytes can be accessed at this address and then the eight bits of the accessed address are output on its eight data ports. EPROM memory chips (27 / 27C...) EPROM stands for Erasable Programmable Read Only Memory. "Erasable" means that the data on it can be removed. "Programmable" means that a program or data can be programmed (burned) into this chip. "Read Only Memory" means that this type of memory can be read out but not programmed in

Computers use a fixed number of bits to represent an integer.  The commonly-used bit-lengths for integers are 8-bit, 16-bit, 32-bit or 64-bit.  Besides bit-lengths, there are two representation schemes for integers: Unsigned Integers: can represent zero and positive integers. Signed Integers: can represent zero, positive and negative integers. n-bit Unsigned Integers Unsigned integers can represent zero and positive integers, but not negative integers. Example 1: Suppose that n=8 and the binary pattern is 0100 0001B, the value of this unsigned integer is 1×2^0 + 1×2^6 = 65D. Example 2: Suppose that n=16 and the binary pattern is 0001 0000 0000 1000B, the value of this unsigned integer is 1×2^3 + 1×2^12 = 4104D. Signed Integers Signed integers can represent zero, positive integers, as well as negative integers. Three representation schemes are available for signed integers: Sign-Magnitude representation 1's Complement representation 2's Complement

Data Representation Integer Representation(Signed and Un-signed Numbers)

Number Systems Human beings use decimal (base 10) number systems for counting and measurements. Computers use binary (base 2) number system, as they are made from binary digital components (known as transistors) operating in two states - on and off. In computing, we also use hexadecimal (base 16) or octal (base 8) number systems, as a compact form for represent binary numbers. Decimal (Base 10) Number System Decimal number system has ten symbols: 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9, called digits. It uses positional notation. That is, the least-significant digit (right-most digit) is of the order of 10^0 (units or ones), the second right-most digit is of the order of 10^1 (tens), the third right-most digit is of the order of 10^2 (hundreds), and so on.  For example,                                735 = 7×10^2 + 3×10^1 + 5×10^0 Binary (Base 2) Number System Binary number system has two symbols: 0 and 1, called bits.  It is also a positional notation. for example,

In computers, encoding is the process of putting a sequence of characters (letters, numbers, punctuation, and certain symbols) into a specialized format for efficient transmission or storage. Decoding is the opposite process -- the conversion of an encoded format back into the original sequence of characters. Encoding and decoding are used in data communications, networking, and storage. The code used by most computers for text files is known as ASCII (American Standard Code for Information Interchange). ASCII can depict uppercase and lowercase alphabetic characters, numerals, punctuation marks, and common symbols. Other commonly-used codes include Unicode, BinHex and Uuencode. In data communications, Manchester encoding is a special form of encoding in which the binary digits (bits) represent the transitions between high and low logic states. Operation Code (Opcode) It specifies the operation to be performed. The operation of the CPU is determined by the instructi

A set of instructions that perform a task is called a program usually a program is stored in the memory. The processor then fetches the instructions comprising the program from memory one at a time and perform the desired operations. The computer is under control of stored program,except for the possibility of external interruption from the operator or by I/O devices connected to the machine. The operation of the CPU is determined by the instructions it executes. These instructions are referred to as machine instructions or computer instructions. The collection of different instructions that the CPU can execute is referred to as the CPU‟s instruction set. Example Program                           Compute (X+Y)Z                           MVI B, X                           MVI A,Y                           ADD B                            STA 5000H                           HLT Assembly Language Programming Types of Instructions An assembly language program i

Steps involved in instruction execution in CPU Instructions and data are the information fed to a computer. Instructions are explicit commands that Govern the transfer of information within a computer as well as between the computer and its I/O devices. Specify the arithmetic and logic operations to be performed. A set of instructions that perform a task is called a program usually a program is stored in the memory. The processor then fetches the instructions comprising the program from memory one at a time and perform the desired operations. The computer is under control of stored program, except for the possibility of external interruption from the operator or by I/O devices connected to the machine. The operation of the CPU is determined by the instructions it executes. These instructions are referred to as machine instructions or computer instructions. The collection of different instructions that the CPU can execute is referred to as the CPU‟s instruction set. Ea

The main memory contains a large number of semiconductor storage cells each capable of storing one bit of information. These cells are processed in groups of fixed size called words. The main memory is organized so that the contents of one word containing n bits can be stored or retrieved in one basic operation. To provide easy access to any word in memory, a distinct address is associated with each word location. A given word is accessed by specifying its address and issuing a control command that starts the storage or retrieval process. The time required to access one word is called memory access time. The number of bits in each word is often referred to as the word length of the computer. Large computers have usually 32 or more bits in a word and micro computer word lengths range from 8 to 32 bits. The capacity of the main memory is few hundred thousand words, whereas medium and large machines normally have millions of words. Data are manipulated within a machine in uni

RISC CISC  Emphasis on software  Emphasis on hardware  Single-clock, reduced instruction only  Includes multi-clock complex instructions  Register to register: Memory-to-memory: "LOAD" and "STORE" are independent instructions "LOAD" and "STORE" incorporated in instructions  large code sizes, Low cycles per second Small code sizes, High cycles per second  Spends more transistors on memory registers Transistors used for storing complex instructions  uses small and limited number of instructions. CISC chips have a large amount of different and complex instructions. RISC processors uses simple addressing modes.  CISC machines generally make use of complex addressing modes.  RISC machines uses hardwired control unit.  CISC machines uses micro-program control unit. 

RISC processors only use simple instructions that can be executed within one clock cycle. Thus, the "MULT" command described above could be divided into three separate commands:  "LOAD," which moves data from the memory bank to a register, "PROD," which finds the product of two operands located within the registers "STORE," which moves data from a register to the memory banks.                          LOAD A, 2:3                       LOAD B, 5:2                       PROD A, B                       STORE 2:3, A More RAM is needed to store the assembly level instructions. The compiler must also perform more work to convert a high-level language statement into machine code.  To execute each instruction, if there is separate electronic circuitry in the control unit, which produces all the necessary signals. It is also called hard-wired approach.  pipelining: a techique that allows for simultaneous execution of parts,